1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device with a nonvolatile semiconductor memory cell.
2. Description of the Background Art
Prior art related to a nonvolatile semiconductor memory cell using a ferroelectric capacitor for a memory cell is disclosed in Japanese Patent Publication No. 7-34315. This is a nonvolatile semiconductor memory cell MC0 having a structure in which the electrodes at opposite sides of a ferroelectric capacitor C0 are connected to a first bit line BL and a second bit line /BL via a switching device (here, N channel MOS transistors NT1 and NT2), as shown in FIG. 7.
This conventional nonvolatile semiconductor memory cell MC0 has the advantage that noise and the like do not reach ferroelectric capacitor C0 since both ends of ferroelectric capacitor C0 are isolated from first and second bit lines BL and /BL by N channel MOS transistors NT1 and NT2.
Data is read out in a self-referencing manner in which data stored in ferroelectric capacitor C0 is determined on the basis of the polarization property thereof. Therefore, data can be read out stably even when the polarization property of ferroelectric capacitor C0 differs for each cell.
However, the conventional nonvolatile semiconductor memory cell shown in FIG. 7 requires two N channel MOS transistors NT1 and NT2 and one ferroelectric capacitor C0 to form one memory cell, i.e., to store data of 1 bit. This means that extra area is required in comparison to the case where one memory cell storing 1-bit data is formed of one transistor and one ferroelectric capacitor.